View source for Computer Architecture Lab/SS2013/Group3/Assignment2

== BraveMIPS Instruction Set Architecture ==

=== BraveMIPS Instruction Set Format ===

The format of the 32bit MIPS I processor is kept:

{| class="wikitable"
|-
! Type || colspan=6| -31- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; format (bits) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; -0-
|- align=center
| '''R''' || opcode (6) || rs (5) || rt (5) || rd (5) || shamt (5) || funct (6)
|- align=center
| '''I''' || opcode (6) || rs (5) || rt (5) ||colspan=3| immediate (16)
|- align=center
| '''J''' || opcode (6) ||colspan=5| address (26)
|}
(same as on [[Wikipedia:MIPS architecture#MIPS I instruction formats|Wikipedia Page]])

=== BraveMIPS Instruction Set ===

The instruction set is focused on integer-based instructions and it essentially consists of a subset of the MIPS Instruction Set (see the full set on [[Wikipedia:MIPS architecture#MIPS assembly language|Wikipedia]], section "Integer"). Other instructions might be added as project progresses.

{| class=wikitable
|-
!Category !! Name !! Instruction syntax !! Meaning !!colspan=3| Format/opcode/funct !! Notes/Encoding
|-
|rowspan=5| Arithmetic
||Add           || add $d,$s,$t    || $d = $s + $t || R || 0 || 20<sub>16</sub> || adds two registers, executes a trap on overflow<br><pre>000000ss sssttttt ddddd--- --100000</pre>
|-
| Subtract      || sub $d,$s,$t    || $d = $s - $t || R || 0 || 22<sub>16</sub> || subtracts two registers, executes a trap on overflow<br><pre>000000ss sssttttt ddddd--- --100010</pre>
|-
| Add immediate || addi $t,$s,C || $t = $s + C (signed) || I || 8<sub>16</sub> || - || Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow<br><pre>001000ss sssttttt CCCCCCCC CCCCCCCC</pre>
|-
| Multiply      || mult $s,$t        || LO = (($s * $t) << 32) >> 32;<br> HI = ($s * $t) >> 32; || R || 0 || 18<sub>16</sub> || Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
|-
| Divide        || div $s, $t       ||  LO = $s / $t  &nbsp;&nbsp;&nbsp;   HI = $s % $t         || R || 0 || 1A<sub>16</sub> || Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.
|-
|rowspan=2| Data Transfer 
|| Load word || lw $t,C($s)     || $t = Memory[$s + C] || I || 23<sub>16</sub> || - || loads the word stored from: MEM[$s+C] and the following 3 bytes. 
|-
| Store word || sw $t,C($s)   || Memory[$s + C] = $t || I || 2B<sub>16</sub> || - || stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion. 
|-
|rowspan=8| Logical 
||And                    || and $d,$s,$t    || $d = $s & $t || R || 0 || 24<sub>16</sub> || Bitwise operation and<br><pre>000000ss sssttttt ddddd--- --100100</pre>
|-
| And immediate          || andi $t,$s,C    || $t = $s & C || I || C<sub>16</sub> || - || Leftmost 16 bits are padded with 0's<br><pre>001100ss sssttttt CCCCCCCC CCCCCCCC</pre>
|-
| Or                     || or $d,$s,$t     || $d = $s &#124; $t || R || 0 || 25<sub>16</sub> || Bitwise or
|-
| Or immediate            || ori $t,$s,C || $t = $s &#124; C || I || D<sub>16</sub> || - || Leftmost 16 bits are padded with 0's
|-
| Exclusive or            || xor $d,$s,$t    || $d = $s ^ $t || R || 0 || 26<sub>16</sub> ||
|-
| Nor                      || nor $d,$s,$t    || $d = ~ ($s &#124; $t) || R || 0 || 27<sub>16</sub> || Bitwise nor
|-
| Set on less than           || slt $d,$s,$t   || $d = ($s < $t) || R || 0 || 2A<sub>16</sub> || Tests if one register is less than another.
|-
| Set on less than immediate || slti $t,$s,C || $t = ($s < C) || I || A<sub>16</sub> || - || Tests if one register is less than a constant.
|-
|rowspan=2| Bitwise Shift
|| Shift left logical    || sll $d,$t,shamt || $d = $t << shamt || R || 0 || 0 || shifts shamt number of bits to the left (multiplies by <math>2^{shamt} </math>)
|-
| Shift right logical    || srl $d,$t,shamt || $d = $t >> shamt || R || 0 || 2<sub>16</sub> || shifts shamt number of bits to the right - zeros are shifted in (divides by <math>2^{shamt} </math>). Note that this instruction only works as division of a two's complement number if the value is positive.
|-
|rowspan=2| Conditional branch
|| Branch on equal || beq $s,$t,C || if ($s == $t) go to PC+4+4*C || I || 4<sub>16</sub> || - || Goes to the instruction at the specified address if two registers are equal.<br><pre>000100ss sssttttt CCCCCCCC CCCCCCCC</pre>
|-
| Branch on not equal || bne $s,$t,C || if ($s != $t) go to PC+4+4*C || I || 5<sub>16</sub> || - || Goes to the instruction at the specified address if two registers are ''not'' equal.
|-
|rowspan=2| Unconditional jump 
|| Jump         || j C || PC = PC+4[31:28] . C*4 || J || 2<sub>16</sub> || - || Unconditionally jumps to the instruction at the specified address.
|-
| Jump register || jr $s   || goto address $s || R || 0 || 8<sub>16</sub> || Jumps to the address contained in the specified register
|}

=== BraveMIPS Assembler ===

The assembler is based around JFlex and CUP (Java implementations of a lexer and parser).
Until now I have successfully "compiled" the lexer file, whose source is found here: [https://github.com/BogdanSorlea/BraveMIPS-FPGA/blob/master/assembler/jflex/bravemips_scanner.l /assembler/jflex/bravemips_scanner.l]
I still need to get the CUP-specific syntax to run and integrate the two.

NOTE: in the worst case scenario, I might implement a pure Java String manipulation-based assembler (if I will have problems with JFlex and CUP).
{{CourseCat}}