View source for Digital Logic 1/Digital Signals and Logic Symbols

=Basic Ideas and Concepts=
*Learn what is referred to as a "digital" circuit
*Learn the respective logic gates and symbols associated
*Learn the functionality of each logic gate

=Digitization=
When we say we have a "digital" circuit, it means that we create an entire new domain that is purely represented by an analog signal. What that means is, referring back to our basic circuit of a voltage source and a resistor, we can say that the different voltage levels can represent a "low" or "high". Using electrical and computer engineering conventions, we classify a logic "high" as anywhere from 4.5 volts to 5.0 volts and a logic "low" as anywhere from 0.1 to 0.5 volts.

So basically, we say that a 0 is inputted when the voltage is between 0.1-0.5 volts and a 1 if the voltage is 4.5-5 volts. Ideally however, we want 0.0 and 5.0 volts to represent 0 and 1 respectively and pictorially is represented below.

<table><tr>
<td>high 1 or on</td><td>low 0 or off</td>
</tr><tr>
<td>{{EE_DMM||dc|+|5|p|0|0}}</td><td>{{EE_DMM||dc|+|0|p|0|0}}</td>
</tr>
</table>

With this in mind, we can now move on and discuss logic gates which form the foundation of combinational circuits and analysis.

=Logic Gates=
Below are all the different logic symbols that are used to design and implement digital circuits.

{| class="wikitable"
! Type !! Distinctive shape !! Rectangular shape !! Mathematical<br>Representation !! Truth table
|-
| '''[[w:AND Gate|AND Gate]]'''
| [[Image:AND ANSI.svg|AND symbol]]
| [[Image:AND IEC.svg|AND symbol]]
| <math>A \cdot B</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A AND B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 1
|}
|-
| '''[[w:OR gate|OR Gate]]'''
| [[Image:OR ANSI.svg|OR symbol]]
| [[Image:OR IEC.svg|OR symbol]]
| <math>A+B \! </math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A OR B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 1
|}
|-
| '''[[w:NOT gate | NOT Gate]]'''
| [[Image:NOT ANSI.svg|NOT symbol]]
| [[Image:NOT IEC.svg|NOT symbol]]
| <math>\overline{A}</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || NOT A
|- bgcolor="#ddffdd" align="center"
|0 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 0
|}
|-
| colspan="5" |
{| class="wikitable collapsible collapsed"
! Note about NOT gate
|-
|
In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'', and is used in logic diagrams to indicate a logical inversion between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or high voltage level = 0), respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (high voltage level = 0) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and rectangular-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful.
|}
|-
| '''[[w:NAND gate|NAND Gate]]'''
| [[Image:NAND ANSI.svg|NAND symbol]]
| [[Image:NAND IEC.svg|NAND symbol]]
| <math>\overline{A \cdot B}</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A NAND B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 0
|}
|-
| '''[[w:NOR gate|NOR Gate]]'''
| [[Image:NOR ANSI.svg|NOR symbol]]
| [[Image:NOR IEC.svg|NOR symbol]]
| <math>\overline{A + B}</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A NOR B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 0
|}
|-
| colspan="5" |
|-
| '''[[w:XOR gate|XOR Gate]]'''
| [[Image:XOR ANSI.svg|XOR symbol]]
| [[Image:XOR IEC.svg|XOR symbol]]
| <math>A \oplus B</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A XOR B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 0
|}
|-
| '''[[w:XNOR gate|XNOR Gate]]'''
| [[Image:XNOR ANSI.svg|XNOR symbol]]
| [[Image:XNOR IEC.svg|XNOR symbol]]
| <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math>
|
{| class="wikitable" align=right
|- bgcolor="#ddeeff" align="center"
|colspan=2|'''INPUT''' || '''OUTPUT'''
|- bgcolor="#ddeeff" align="center"
| A || B || A XNOR B
|- bgcolor="#ddffdd" align="center"
|0 || 0 || 1
|- bgcolor="#ddffdd" align="center"
|0 || 1 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 0 || 0
|- bgcolor="#ddffdd" align="center"
|1 || 1 || 1
|}
|}
{{courseCat}}